1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly to a semiconductor device having a higher tolerance to metal pollution and a method of manufacturing the semiconductor device.
2. Description of the Background Art
A semiconductor device having an SOI structure (hereinafter referred to as an SOI device) to be formed on an SOI substrate in which a buried oxide film and an SOI (Silicon On Insulator) layer are provided on a silicon substrate is characterized in that a parasitic capacitance can be reduced, an operation can be carried out at a high speed and power consumption can be reduced, and is used for portable equipment and the like.
In order to implement a high speed operating circuit, a technique for reducing a resistance is essential. As the technique for reducing a resistance, generally, a method of forming a metal compound layer (silicide layer) in self-alignment in a gate wiring or a source-drain region of a transistor constituting the circuit.
For example, as shown in FIG. 83 of Japanese Patent Application Laid-Open No. 6-204334 (1994), a metal layer such as Ti (titanium) or Co (cobalt) is deposited through sputtering or the like over an upper portion of a gate electrode formed of polysilicon and a source-drain region and a heat treatment is carried out for a short time so that a silicide layer is formed. In general, it has been known that the metal layer does not form the silicide layer over an isolating film, an oxide film such as a side wall oxide film of a gate electrode, and a nitride film at this time.
Depending on the conditions of the heat treatment or the kind of an insulating film, however, a metallic element such as Co is diffused into the insulating film and reaches a silicon layer provided under the insulating film so that a silicide is formed therein in some cases.
For example, there is a problem in that a circuit malfunctions due to an increase in a junction leakage current when the silicide is formed in a PN junction region.
In recent years, moreover, a wiring material tends to be changed from a conventional Al (aluminum)-Cu (copper) alloy wiring to a Cu wiring or the like due to a reduction in a resistance of a wiring. Correspondingly, it has been reported that a characteristic of a device is deteriorated due to the diffusion of Cu.
In addition, the number of process steps is increased with microfabrication of a semiconductor device and multilayered wiring. Consequently, the metal pollution often occurs. When a metal pollutant is segregated into a junction interface, the junction leakage current is increased and the circuit malfunctions as described above.
A conventional silicide process will be described with reference to FIGS. 62 to 65.
First of all, an SOI substrate 10 in which a buried oxide film 2 and an SOI layer 3 are provided on a silicon substrate 1 is prepared as shown in FIG. 62 and a trench isolation oxide film ST1 is selectively formed as an isolating film in a surface of the SOI layer 3, thereby defining a region QR forming a MOS transistor and a region RR forming a resistive element.
A trench isolation oxide film ST1 is also referred to as a shallow trench isolation oxide film (ST1) and has a well region WR provided thereunder so that elements are not electrically isolated completely from each other. In some cases, therefore, the trench isolation oxide film ST1 is also referred to as a partial isolation oxide film (PT1).
After the trench isolation oxide film ST1 is formed, a gate oxide film GO and a gate electrode GT are selectively formed on the SOI layer 3 of the MOS transistor region QR.
Then, a resist mask R1 is formed such that the region QR is to be an opening, and an impurity ion of the same conductivity type as that of the source-drain region in the SOI layer is implanted by using the gate electrode GT as a mask. Thus, an extension region EX is formed in self-alignment.
The extension region EX is a shallower diffusion region than a source-drain region which is to be formed at a subsequent step, and is formed by implanting the impurity ion in a lower concentration than that of the source-drain region or in substantially the same concentration as that of the source-drain region such that it acts as a part of the source-drain region.
At a step shown in FIG. 63, next, a side wall spacer SW is formed on a side surface of the gate electrode GT, a resist mask R2 is formed such that the regions QR and RR are to be openings, and an impurity ion is implanted into the SOI layer 3 to form a source-drain region SD in self-alignment. At this time, the impurity is also implanted into the resistive element region RR so that a resistive layer RL is formed.
At a step shown in FIG. 64, subsequently, an insulating film IF is selectively formed on the SOI layer 3 in the region RR to prevent the formation of a silicide layer. Then, a metal layer such as Ti or Co is deposited through sputtering or the like and a silicide reaction is promoted by a heat treatment.
The silicide reaction is achieved by causing an exposed silicon layer to react to the metal layer provided thereon through a beat treatment at a low temperature for a short time. Since the metal layer formed on an insulating film such as an oxide film is not silicided, it is removed in a subsequent removing process. Then, a silicide film having a stable structure is formed through a second heat treatment.
FIG. 64 shows a state obtained after an unreacted metal film is removed, and a silicide layer SS is formed over the source-drain region SD, the gate electrode GT and the resistive layer RL. A silicide layer SS is formed in two positions interposing an insulating film IF over the resistive layer RL and acts as two electrodes of the resistive element.
At a step shown in FIG. 65, then, an interlayer insulating film IZ is formed on the SOI layer 3, and a plurality of contact portions CH reaching the silicide layer SS formed on the source-drain layer SD and the resistive layer RL are provided through the interlayer insulating film IZ. Thus, an SOI device 90 is constituted.
Referring to FIGS. 62 to 65, the SOI device 90 formed on the SOI substrate 10 has been described. FIG. 66 shows a bulk device 90A formed on a bulk silicon substrate 1.
In the bulk device 90A, a deeper trench isolation oxide film ST2 is provided in place of the trench isolation oxide film ST1. Since other structures are the same as those of the SOI device 90 shown in FIG. 65, the same structures have the same reference numerals and repetitive description will be omitted.
As described above, the silicide reaction causes the exposed silicon layer to react to the metal layer provided thereon through the heat treatment (first heat treatment) at a low temperature for a short time and the unreacted metal film is removed, and the silicide film having a stable structure is then formed through the second heat treatment. There is a possibility that a metal constituting the metal film might be diffused into the insulating film through the first heat treatment or the unreacted metal film might be removed insufficiently to cause the metal to remain in a very small amount over the insulating film and to be diffused into the insulating film through the second heat treatment or a heat treatment in a subsequent process. In such a case, the metal layer reaching a surface of the silicon layer forms a silicide. For example, in the case in which the silicide is formed in a PN junction region, a junction leakage current is caused. In the case in which the silicide is formed in the vicinity of an interface between a gate insulating film and a silicon layer, reliability of the gate insulating film is deteriorated.
As shown in FIG. 66, it is apparent that the same problem arises in the device 90A formed on the bulk silicon layer 1.